1. Technical Field
The disclosures herein relate to a semiconductor memory apparatus and, more particularly, to a circuit for generating an on-die termination control signal to operate an on-die termination circuit of a semiconductor memory apparatus.
2. Related Art
Conventional on-die termination control refers to an operation which allows a driver to have impedance identical to a reference impedance regardless of PVT (process, voltage and temperature) fluctuations. In order to perform the on-die termination control, an on-die termination circuit is provided in a semiconductor memory apparatus. In addition, a circuit for generating an on-die termination control signal is provided in the semiconductor memory apparatus in order to allow the on-die termination circuit to perform the on-die termination control.
As shown in FIG. 1, an exemplary circuit for generating an on-die termination control signal includes a first pulse generator 11, a first NOR gate NR1, a first inverter IV1, a second inverter IV2, a NAND gate ND1, a third inverter IV3, an oscillator 12, a second pulse generator 13, a counter 14, a second NOR gate NR2 and a fourth inverter IV4.
Hereinafter, the operation of the conventional circuit for generating the on-die termination control signal will be described with reference to FIGS. 1 and 2.
When an auto-refresh pulse signal (AREFP) is generated according to an auto-refresh command or a self-refresh signal (SREF) is deactivated, a first internal signal (INT_CALP1) is generated through the first NOR gate NR1 and the first inverter IV1. The first internal signal (INT_CALP1) is output as an on-die termination control signal (ODT_CALP) through the second NOR gate NR2 and the fourth inverter IV4.
Meanwhile, if a system stabilizing signal (RES) is activated and a counting limit signal (CAL_MAX) is deactivated, then an oscillator enable signal (OSC_EN) is activated through the first NAND gate ND1 and the third inverter IV3. The system stabilizing signal (RES) is used to notify a semiconductor memory device of the stable operation of the system, that is, to notify the situation that a GPU (graphic processing unit) or a CPU (central processing unit) stably outputs clock signals. In addition, the counting limit signal (CAL_MAX) is activated when the counter 14 counts to a predetermined number. In the initial operation, the counting limit signal (CAL_MAX) is deactivated in a low level. As the oscillator enable signal (OSC_EN) is activated, the oscillator 12 generates a control signal generating clock (CAL_CLK).
The second pulse generator 13 is activated according to the system stabilizing signal (RES) and generates a pulse, that is, the second internal signal (INT_CALP2) by using the control signal generating clock (CAL_CLK). The second internal signal (INT_CALP2) is output as an on-die termination control signal (ODT_CALP) through the second NOR gate NR2 and the fourth inverter IV4.
Meanwhile, the counter 14 counts the number of second internal signals (INT_CALP2) of the second pulse generator 13, that is, the generating number of pulses by using the control signal generating clock (CAL_CLK). The counter 14 activates the counting limit signal (CAL_MAX) in a high level when the count value reaches a predetermined level (for example, 30 times).
As the counting limit signal (CAL_MAX) is activated in a high level, the oscillator enable signal (OSC_EN) is deactivated, so that the operation of the oscillator 12 is stopped and the second pulse generator 13 does not generate the second internal signal (INT_CALP2).
In a conventional semiconductor memory apparatus, a frequency/voltage switching (FVS) period exists in a self-refresh period where the self-refresh signal (SREF) is activated. The FVS period is for switching voltage or frequency to save power consumption according to the operational mode change. Since the voltage or the frequency is switched in the FVS period, the voltage or the frequency is unstable in the FVS period.
In a first case (case 1) illustrated in FIG. 2, the on-die termination control signal (ODT_CALP) can be generated according to the auto-refresh command generated in the FVS period (A). Since the voltage or the frequency is unstable in the FVS period, the toggling of the system stabilizing signal (RES) may occur. Due to the toggling of the system stabilizing signal (RES), the on-die termination control signal (ODT_CALP) is generated several times (B).
In a second case (case 2), the on-die termination control signal (ODT_CALP) can be generated according to the auto-refresh command generated in the self-refresh period (C). If the second case exists, then it is not the self-refresh mode since the clock enable signal CKE is activated. But, an internal circuit of the semiconductor apparatus maintains a self-refresh mode.
In a third case (case 3), as indicated by “D”, the on-die termination control signal (ODT_CALP), which is generated according to the auto-refresh command, may collide with the on-die termination control signal (ODT_CALP), which is generated when the self-refresh period ends. In this case, the on-die termination enable signal (ODT_EN) is activated when the self-refresh period ends. Accordingly, the on-die termination circuit, which performs the on-die termination control, operates so that a supply voltage VDDQ can be temporarily dropped (E).
In a fourth case (case 4), the on-die termination control signal (ODT_CALP) is generated one time according to the auto-refresh command (F). However, since the self-refresh period ends and the supply voltage VDDQ is stabilized after being temporarily dropped, it is necessary to perform the on-die termination control several times as represented in “B”.
However, a conventional circuit for generating the on-die termination control signal has the following problems: First, since the on-die termination control signal is generated in the self-refresh period including the FVS period to perform the on-die termination control, the accuracy of the on-die termination control is significantly lowered. Second, the on-die termination control signal caused by the auto-refresh command may collide with the on-die termination control signal generated when the self-refresh period ends so that the on-die termination control cannot be performed or the accuracy thereof is significantly lowered. Third, since the on-die termination control signal is generated one time after the self-refresh period ends, the on-die termination control is performed one time so that the control result does not reflect actual voltage and frequency variation.